1. Field of the Invention
The present invention relates to a semiconductor integrated circuit including an interface circuit that enables handling of the input/output of a signal to and from an external circuit operating at a different power voltage, and particularly, to a semiconductor integrated circuit that cuts the operation of the interface circuit at a no access mode when no access is effectuated with the external circuit.
2. Description of the Related Art
In recent years, there has been a trend towards lower voltages and higher integration in semiconductor integrated circuits like ICs and LSIs used in electronic equipment to enable low power consumption and high speed operation of various types of electronic equipment. However, considering the characteristics of each type of device, it is extremely difficult to change all of the operation voltages of semiconductor integrated circuits to a lower level simultaneously. Therefore, the need arises for interconnecting these semiconductor integrated circuits through internal interface circuits to account for operating a plurality of semiconductor integrated circuits at different power voltages.
For example, it is conceivable that in a PCI (Peripheral Component Interconnect) card for use in personal computers, the power source voltage of the card itself is 3.3 V, and that the power source voltage of other cards connected to a bus line connecting the PCI card is 5 V. In that case, an interface circuit is required, that allows inputting an output signal from an external circuit operated at 5 V to an IC of a PCI card operated at 3.3 V without causing any problems.
In general, the absolute value of the maximum rated voltage (hereafter referred to as the withstanding voltage) between the drain and the gate of the MOS transistor in semiconductor integrated circuits operated at 3.3 V will be higher than the power source voltage of 3.3 V, but to conform with high speed operation, will be lower than the withstanding voltage of the MOS transistor in the semiconductor integrated circuit operated at 5 V, and thus, is often lower than 5 V. In such a case, it will not be possible to input the output signal of a semiconductor integrated circuit operating at 5 V into a semiconductor integrated circuit operating at 3.3 V.
Here, an interface circuit is proposed that solves the problem of the withstanding voltage when connecting an external circuit operated at a different power source voltage. FIG. 4 is a circuit diagram showing part of the configuration of such a conventional interface circuit. As shown in FIG. 4, this interface circuit includes an external input/output terminal (pad) PD, an input buffer IB, and an n-channel MOS transistor QN10 having a drain/source connected between the pad PD and the input buffer IB.
A power source voltage of 3.3 V is supplied to the input buffer IB, and the gate of the transistor QN10. On the other hand, a signal of 0 V to 5 V is input at the pad PD. The transistor QN10 functions as a transfer gate or a transmission gate that exchanges the output signal of the 5 V circuit adjusting it to the 3.3 V circuit.
FIG. 5 is a view showing the relationship between the pad potential and the input/output potential of the transfer gate. In FIG. 5, the lateral axis shows the pad potential VPD, the vertical axis shows the drain potential VD and the source potential Vs of the transistor QN10 that functions as a transfer gate. In the case where the pad potential VPD changes in the range between 0 V and 5 V, the drain potential VD of the transistor QN10 changes following the former.
On the other hand, the source potential Vs of the transistor QN10, in the case where the threshold voltage of the transistor QN10 is shown as VTN, does not exceed (3.3−VTN) V, even if the pad potential VPD exceeds 3.3 V. Accordingly, the transfer gate exchanges the output signal of the 5 V circuit into a potential that is lower than the potential of the 3.3 V power source potential, and it can thus be safely supplied to the input buffer IB.
Here, in the case where the pad potential VPD is 5 V, the voltage VDG between the drain and the gate of the transistor QN10 is 1.7 V, and in the case where the pad potential VPD is 0 V, the voltage VDG between the drain and the gate of the transistor QN10 is −3.3 V. On the other hand, the withstanding voltage of the transistor QN10 being larger than 3.3 V, the transistor QN10 will not be destroyed.
However, to attempt to further lower the electrical power consumption of the semiconductor integrated circuit, it is conceivable to reduce the power source voltage of the internal circuits other than the interface circuit to for example 1.8 V, while keeping the power source voltage of the interface circuit at 3.3 V. In the case of such a semiconductor integrated circuit, in the no-access mode where no access takes place to and from the external circuit, the supply of a 3.3 V power source is interrupted, so as to stop the interface circuit from operating, which is advantageous from the point of view of lowering the power consumption.
However, when using an interface circuit such as the interface circuit shown in FIG. 4, a problem such as the one described below arises. That is to say, as shown in FIG. 6, when the power source supply of 3.3 V is interrupted, the gate potential of the transistor QN10 becomes 0 V, and thus, in the case where the pad potential VPD is 5 V, the voltage VDG between the drain and the gate of the transistor QN10 also becomes 5 V. On the other hand, the withstanding voltage of the transistor QN10, even though larger than 3.3 V is smaller than 5 V, thus leading to the deterioration or destruction of the transistor QN10.
As a related art document, in Japanese Unexamined Patent Application Publication No. 2000-77996 (First Page, FIG. 2), an interface circuit, that is a voltage tolerant circuit, is disclosed for preventing a leak current, this being a substantial problem in whichever voltage transition status. However, nothing is disclosed with respect to preventing the deterioration and destruction of the transistor when the main power source supply to the interface circuit is interrupted.
In view of the above issues, the present invention is intended to prevent the deterioration and destruction of the transistor when the main power source supply to the interface circuit is interrupted in a semiconductor integrated circuit including an interface circuit that allows handling of the input and output of signals with an external circuit that operates at a different power source voltage.